In the integrated circuit industry today, hundreds of thousands of semiconductor devices are built on a single chip. Contact resistances between functioning areas of a CMOD device, such as a source or drain region, is critical to the functioning of a CMOS device, for example a transistor. For example, metal interconnect features are formed to connect source and drain regions to other parts of a functioning semiconductor device. Source and drain regions of a transistor are doped portions of a semiconductor substrate, for example single crystal silicon. The source and drain regions are typically formed by implanting ions in the silicon substrate to achieve n-doped regions or p-doped regions. To prevent the contamination of the silicon substrate by contacting metal interconnects, an intermediate layer of a metal silicide is formed over the silicon substrate, for example, titanium silicide or cobalt silicide. Metal silicides are thermally stable at higher temperatures and prevent metals from diffusing into the silicon substrate which will alter electrical properties.
One requirement of the metal silicide is the necessity for low sheet resistance or contact resistance to the silicon substrate. In this regard, cobalt silicide (e.g., CoSi2) and titanium silicide (TiSi2) have the lowest resistivity and therefore provide a lower contact resistance to the silicon semiconductor substrate. The severity of the effect of increased resistance on the drain side of the transistor depends on whether the transistor is operating in the saturated region or the linear region, where the reduction of drain voltage has less effect if operation is in the saturated region. Increased contact resistance on the source side of the transistor is generally more severe, reducing the effective gate voltage and severely degrading device performance. It has been found that self aligned silicides (salicides) covering the entire source/drain area is the one of the most effective solutions to decreasing contact resistance and improving device performance allowing device scaling below 0.25 microns.
One problem in forming salicides having line widths less than about 0.5 microns, is the tendency of titanium silicides to agglomerate when formed overlying gate, source, and drain regions and subjected to high annealing temperatures, typically using a rapid thermal anneal (RTA), also referred to as a rapid thermal process (RTP). For example, in the formation of titanium silicide, typically a two-step process is required to form the low electrical resistance phase of titanium silicide, frequently requiring annealing temperatures of up to 800° C. In smaller line width areas, the titanium silicide has difficulty achieving the nucleation and growth of the crystalline phase required for low electrical resistance, requiring higher annealing temperatures, which frequently causes agglomeration of the silicide. Consequently, cobalt silicide is a preferred material for forming salicides for sub-quarter micron devices since the required phase transformation to form the low electrical resistance crystalline phase takes place at lower temperatures, for example, from about 600° C. to about 700° C. without the problem of silicide agglomeration.
In a typical salicide process, a metal, for example titanium or cobalt is deposited to cover the gate, source and drain regions. The metal is then subjected to a two step high temperature anneal where a metal silicide is formed by the diffusion of silicon from underlying areas including silicon or polysilicon into the overlying metal area thereby forming metal silicides. Carrying out the annealing process in nitrogen causes formation of metal nitrides within the metal, for example titanium nitride, slowing the silicon diffusion to prevent what is referred to as bridging, where silicon diffuses into the sidewall regions of the deposited metal along the gate causing a short electrical circuit between the gate region and the source/drain region. The likelihood of bridging increases as the annealing temperature is increased, providing another factor favoring the use of cobalt silicide at least for the formation of salicides over the gate and source/drain regions.
Following formation of the silicided areas over the gate and source/drain regions, a wet etching process is carried out to etch away remaining metal of metal nitrides from unsilicided areas, to form self aligned silicides (salicides) over the respective gate and source/drain regions. One problem with the prior art wet etching process for forming salicides is the poor selectivity demonstrated by prior art etching solutions including, for example, standard cleaning 1 (SC-1) and SC-2, which are typically used as sequential cleaning solutions including mixtures of NH4OH—H2O2—H2O, and HCL—H2O2—H2O, respectively. Poor selectivity of the wet etching solution of the metal and metal nitride portions with respect to the silicided portions will result in, on the one hand, underetching, where residual metals or metal nitrides remain on the sidewall spacers of the gate structure, and on the other hand, overetching of the silicided portions over the gate and source/drain regions. As a result, non-selective etching causes non-uniformities over the wafer resulting in out of specification electrical resistances including sheet resistances over a large percentage of the silicided wafer areas. In addition, poor etching selectivity can detrimentally affect gate oxide integrity. The problem of poor selectivity is especially a concern with cobalt silicide formed over narrow line width areas where silicide defects caused by overetching have a significant effect on electrical behavior, for example, forming nanometer sized voids, leading to increased junction leakage.
There is therefore a need in the semiconductor processing art to develop a method for a reliable and uniform selective wet etching process to form low sheet resistance salicides over sub-quarter micron semiconductor devices with reliable and uniform electrical behavior.
It is therefore an object of the invention to provide a method for a reliable and uniform selective wet etching to form to form low resistance salicides over sub-quarter micron semiconductor devices thereby improving electrical behavior including sheet resistances while overcoming other shortcomings of the prior art.